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Silicon Labs /Series0 /EZR32WG /EZR32WG230F256R69 /TIMER2 /ROUTE

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Interpret as ROUTE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CC0PEN)CC0PEN 0 (CC1PEN)CC1PEN 0 (CC2PEN)CC2PEN 0 (CDTI0PEN)CDTI0PEN 0 (CDTI1PEN)CDTI1PEN 0 (CDTI2PEN)CDTI2PEN 0 (LOC0)LOCATION

LOCATION=LOC0

Description

I/O Routing Register

Fields

CC0PEN

CC Channel 0 Pin Enable
CC1PEN

CC Channel 1 Pin Enable
CC2PEN

CC Channel 2 Pin Enable
CDTI0PEN

CC Channel 0 Complementary Dead-Time Insertion Pin Enable
CDTI1PEN

CC Channel 1 Complementary Dead-Time Insertion Pin Enable
CDTI2PEN

CC Channel 2 Complementary Dead-Time Insertion Pin Enable
LOCATION

I/O Location

0 (LOC0): Location 0

1 (LOC1): Location 1

2 (LOC2): Location 2

3 (LOC3): Location 3

4 (LOC4): Location 4

5 (LOC5): Location 5

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data